1. Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same.
2. Description of the Related Art
In recent years, design rules in the field of semiconductor devices have been reduced drastically. Conventionally, to shrink the height of standard cells, etc. in a semiconductor device, the semiconductor device has been designed with consideration given to interdiffusion occurring at the boundary between an n-type MIS transistor and a p-type MIS transistor therein (see Patent Document 1, for example).
Interdiffusion occurring due to substrate contact portions, however, has not been sufficiently considered, and the boundaries between the transistors and the substrate contact portions have been designed based on the same rules as the boundary between the n-type MIS transistor and the p-type MIS transistor.
FIG. 20A is a plan view of a conventional semiconductor device having a dual-gate structure, and FIG. 20B is a cross-sectional view taken along the line XX-XX in FIG. 20A.
As shown in FIGS. 20A and 20B, an active region 1a of an n-type MIS transistor (hereinafter referred to as the n-type MIS transistor's active region 1a) and an active region 1b of a p-type MIS transistor (hereinafter referred to as the p-type MIS transistor's active region 1b) are formed on a semiconductor substrate 1 so as to be adjacent to each other with an isolation region 2 interposed therebetween. A substrate contact portion 7 of the n-type MIS transistor (hereinafter referred to as the n-type MIS transistor's substrate contact portion 7) is formed on the semiconductor substrate 1 opposite the p-type MIS transistor's active region 1b with respect to the n-type MIS transistor's active region 1a, while a substrate contact portion 6 of the p-type MIS transistor (hereinafter referred to as the p-type MIS transistor's substrate contact portion 6) is formed on the semiconductor substrate 1 opposite the n-type MIS transistor's active region 1a with respect to the p-type MIS transistor's active region 1b. The isolation region 2 is formed also between the n-type MIS transistor's active region 1a and the n-type MIS transistor's substrate contact portion 7 and between the p-type MIS transistor's active region 1b and the p-type MIS transistor's substrate contact portion 6.
Also, as shown in FIGS. 20A and 20B, an n-type gate electrode 3, into which an n-type impurity has been introduced, is formed over the n-type MIS transistor's active region 1a, while a p-type gate electrode 4, into which a p-type impurity has been introduced, is formed on the p-type MIS transistor's active region 1b. The n-type gate electrode 3 and the p-type gate electrode 4 are connected together on the isolation region 2 located between the n-type MIS transistor's active region 1a and the p-type MIS transistor's active region 1b. An n-type doped layer (an n-type substrate contact region) 6a and an n-type doped layer 3a are formed in the respective surface portions of the p-type MIS transistor's substrate contact portion 6 and n-type gate electrode 3. A p-type doped layer (a p-type substrate contact region) 7a and a p-type doped layer 4a are formed in the respective surface portions of the n-type MIS transistor's substrate contact portion 7 and p-type gate electrode 4.
Furthermore, as shown in FIGS. 20A and 20B, an insulating sidewall spacer 5 is formed on the side walls of the n-type gate electrode 3 and p-type gate electrode 4. Also, contact areas 8 for establishing contact with upper-level interconnects and the like are formed on the n-type MIS transistor's active region 1a, the p-type MIS transistor's active region 1b, the p-type MIS transistor's substrate contact portion 6, and the n-type MIS transistor's substrate contact portion 7.
In the conventional semiconductor device shown in FIGS. 20A and 20B, the length M1 of a part of the n-type gate electrode 3 that protrudes from the n-type MIS transistor's active region 1a toward the n-type MIS transistor's substrate contact portion 7 is set equal to the length N1 of a part of the p-type gate electrode 4 that protrudes from the p-type MIS transistor's active region 1b toward the p-type MIS transistor's substrate contact portion 6.
Moreover, in fabricating the conventional semiconductor device shown in FIGS. 20A and 20B, the width M2 of a p-type substrate contact introducing area (a mask opening area) M3 that defines a region through which a p-type impurity is introduced into the n-type MIS transistor's substrate contact portion 7 is set equal to the width N2 of an n-type substrate contact introducing area (a mask opening area) N3 that defines a region through which an n-type impurity is introduced into the p-type MIS transistor's substrate contact portion 6.
Also, in fabricating the conventional semiconductor device shown in FIGS. 20A and 20B, the distance M4 from the n-type MIS transistor's active region 1a to the p-type substrate contact introducing area M3 is set equal to the distance N4 from the p-type MIS transistor's active region 1b to the n-type substrate contact introducing area N3. In other words, the distance M5 from the n-type MIS transistor's active region 1a to the n-type MIS transistor's substrate contact portion 7 is set equal to the distance N5 from the p-type MIS transistor's active region 1b to the p-type MIS transistor's substrate contact portion 6.
In the above-described conventional semiconductor device shown in FIGS. 20A and 20B, rules that allow the above-mentioned various sizes (M1, M2, M4, M5, N1, N2, N4, and N5) to be sufficiently large are used.